1. Technical Field
The disclosure relates generally to semiconductor fabrication, and more particularly, to forming a dense dielectric layer over the surface of an opening in a porous inter-layer dielectric having an ultra-low dielectric constant.
2. Background Art
Recent rapid advancement in semiconductor technology has brought the advent of very large scale integrated (VLSI) as well as ultra large scale integrated (ULSI) circuits, resulting in integration of more devices into smaller areas on a single semiconductor substrate. In order to further enhance performance of the VLSI and/or ULSI circuits, ultra-low dielectric constant (ULK) materials, such as porous materials, are being used as inter-level dielectrics (i.e., via level dielectrics) and intra-level dielectrics (i.e., line level dielectrics), both referred to as ILDs, herein. ILDs, alternatively known as inter-metal dielectrics (IMDs), are used to further reduce capacitance such as, for example, inter-layer capacitance and intra-layer capacitance that adversely affect circuit performance.
An interconnect structure, which may include metal lines and vias formed in trenches and via openings, respectively, may be formed by first creating a pattern of three-dimensional interconnected openings in the ILD of a porous ULK material. As is known in the art, the structure or pattern may be formed through processes such as lithography and etching, e.g., reactive ion etching (RIE). Subsequently, a metal element or material may be deposited into the trenches and/or via openings of the formed structure pattern to create metal contact lines. Excess metal being deposited on the top surface of the ULK ILD may be removed through a chemical mechanical planarization (CMP) process. On the other hand, it is also known in the art that depositing a copper (Cu) barrier metal (liner), such as tantalum nitride (Ta/TaN), onto a surface of a porous ULK ILD using a conventional process designed or optimized for dense ILD build may cause elements of the metal to penetrate or intrude into the porous material of the ULK ILD. This penetration or intrusion of metal into porous ULK ILDs may cause performance degradation of the metal interconnects formed thereon, as well as degradation of the insulating capability of the ILD. In a worst case, this insulating degradation causes shorting between neighboring elements of the interconnect structure.
Some porous ILDs with dielectric constants in the range of 1.8 to 2.5 also have an interconnected pore structure. The interconnected porosity poses a challenge for the application of advanced liner processes (e.g., thermal and ion-induced atomic layer deposition (iALD), or plasma-enhanced chemical vapor deposition (PECVD)) due to chemical precursors penetrating into the ILD, resulting in degraded back-end-of-line (BEOL) performance, including increased leakage and reduced reliability.
A number of approaches have been employed to address this situation. In one approach, a pore-sealing layer is provided by spin-on chemistries. This approach, however, is not ideal because of the non-uniformity of coverage within and across different features (e.g., sidewall versus the bottom of the opening, different size openings, pattern density dependence, etc.), and the additional burden on the liner process to clean up the bottom of vias to ensure good electrical contact. Furthermore, penetration of the pore-sealing molecules into the ULK dielectric depends on the degree of pore interconnectivity in the ULK. In the case that the ULK ILD has no interconnected pores, the densification of the surface layer is ineffective.